基于MPLAB X xc 配置位设置讲解

作者:fly 发布于:2015-9-29 12:02 分类:嵌入式

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在C:\Program Files\Microchip\xc8\v1.33\docs\chips文件下有相应的配置位介绍,仔细看一下就知道怎么做了。


#pragma config BOREN = OFF, CPD = OFF, FOSC = XT, MCLRE = OFF, WDTE = OFF, CP = OFF, PWRTE = OFF

希望对使用这个XC8的朋友有帮助。

 

18F2520 Support Information


#pragma config Usage


#pragma config <setting>=<named value>


For example:

// Oscillator Selection bits: External RC oscillator, CLKO function on RA6

// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled

// Internal/External Oscillator Switchover bit: Oscillator Switchover mode enabled

#pragma config OSC = RC, FCMEN = ON, IESO = ON

#pragma config <setting>=<literal constant>


For example:

// Oscillator Selection bits: External RC oscillator, CLKO function on RA6

// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled

// Internal/External Oscillator Switchover bit: Oscillator Switchover mode enabled

#pragma config OSC = 0x3, FCMEN = 0x1, IESO = 0x1

#pragma config <register>=<literal constant>


For example:

// Oscillator Selection bits: External RC oscillator, CLKO function on RA6

// Fail-Safe Clock Monitor Enable bit: Fail-Safe Clock Monitor enabled

// Internal/External Oscillator Switchover bit: Oscillator Switchover mode enabled

#pragma config CONFIG1H = 0xC3


For example:

// IDLOC @ 0x200000

#pragma config IDLOC0 = 0xFF

#pragma config Settings


Register: CONFIG1H @ 0x300001


OSC = Oscillator Selection bits

RC External RC oscillator, CLKO function on RA6

ECIO6 EC oscillator, port function on RA6

HS HS oscillator

INTIO67 Internal oscillator block, port function on RA6 and RA7

LP LP oscillator

INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7

HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)

EC EC oscillator, CLKO function on RA6

XT XT oscillator

RCIO6 External RC oscillator, port function on RA6

FCMEN = Fail-Safe Clock Monitor Enable bit

ON Fail-Safe Clock Monitor enabled

OFF Fail-Safe Clock Monitor disabled

IESO = Internal/External Oscillator Switchover bit

ON Oscillator Switchover mode enabled

OFF Oscillator Switchover mode disabled

Register: CONFIG2L @ 0x300002


PWRT = Power-up Timer Enable bit

OFF PWRT disabled

ON PWRT enabled

BOREN = Brown-out Reset Enable bits

NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)

ON Brown-out Reset enabled and controlled by software (SBOREN is enabled)

OFF Brown-out Reset disabled in hardware and software

SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled)

BORV = Brown Out Reset Voltage bits

0 Maximum setting

1

2

3 Minimum setting

Register: CONFIG2H @ 0x300003


WDTPS = Watchdog Timer Postscale Select bits

16384 1:16384

128 1:128

4 1:4

4096 1:4096

2048 1:2048

1024 1:1024

256 1:256

32 1:32

32768 1:32768

16 1:16

8 1:8

1 1:1

8192 1:8192

512 1:512

2 1:2

64 1:64

WDT = Watchdog Timer Enable bit

ON WDT enabled

OFF WDT disabled (control is placed on the SWDTEN bit)

Register: CONFIG3H @ 0x300005


CCP2MX = CCP2 MUX bit

PORTC CCP2 input/output is multiplexed with RC1

PORTBE CCP2 input/output is multiplexed with RB3

PBADEN = PORTB A/D Enable bit

ON PORTB<4:0> pins are configured as analog input channels on Reset

OFF PORTB<4:0> pins are configured as digital I/O on Reset

MCLRE = MCLR Pin Enable bit

ON MCLR pin enabled; RE3 input pin disabled

OFF RE3 input pin enabled; MCLR disabled

LPT1OSC = Low-Power Timer1 Oscillator Enable bit

ON Timer1 configured for low-power operation

OFF Timer1 configured for higher power operation

Register: CONFIG4L @ 0x300006


STVREN = Stack Full/Underflow Reset Enable bit

ON Stack full/underflow will cause Reset

OFF Stack full/underflow will not cause Reset

DEBUG = Background Debugger Enable bit

OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

LVP = Single-Supply ICSP Enable bit

ON Single-Supply ICSP enabled

OFF Single-Supply ICSP disabled

XINST = Extended Instruction Set Enable bit

ON Instruction set extension and Indexed Addressing mode enabled

OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

Register: CONFIG5L @ 0x300008


CP0 = Code Protection bit

OFF Block 0 (000800-001FFFh) not code-protected

ON Block 0 (000800-001FFFh) code-protected

CP1 = Code Protection bit

OFF Block 1 (002000-003FFFh) not code-protected

ON Block 1 (002000-003FFFh) code-protected

CP2 = Code Protection bit

OFF Block 2 (004000-005FFFh) not code-protected

ON Block 2 (004000-005FFFh) code-protected

CP3 = Code Protection bit

OFF Block 3 (006000-007FFFh) not code-protected

ON Block 3 (006000-007FFFh) code-protected

Register: CONFIG5H @ 0x300009


CPB = Boot Block Code Protection bit

OFF Boot block (000000-0007FFh) not code-protected

ON Boot block (000000-0007FFh) code-protected

CPD = Data EEPROM Code Protection bit

OFF Data EEPROM not code-protected

ON Data EEPROM code-protected

Register: CONFIG6L @ 0x30000A


WRT0 = Write Protection bit

OFF Block 0 (000800-001FFFh) not write-protected

ON Block 0 (000800-001FFFh) write-protected

WRT1 = Write Protection bit

OFF Block 1 (002000-003FFFh) not write-protected

ON Block 1 (002000-003FFFh) write-protected

WRT2 = Write Protection bit

OFF Block 2 (004000-005FFFh) not write-protected

ON Block 2 (004000-005FFFh) write-protected

WRT3 = Write Protection bit

OFF Block 3 (006000-007FFFh) not write-protected

ON Block 3 (006000-007FFFh) write-protected

Register: CONFIG6H @ 0x30000B


WRTB = Boot Block Write Protection bit

OFF Boot block (000000-0007FFh) not write-protected

ON Boot block (000000-0007FFh) write-protected

WRTC = Configuration Register Write Protection bit

OFF Configuration registers (300000-3000FFh) not write-protected

ON Configuration registers (300000-3000FFh) write-protected

WRTD = Data EEPROM Write Protection bit

OFF Data EEPROM not write-protected

ON Data EEPROM write-protected

Register: CONFIG7L @ 0x30000C


EBTR0 = Table Read Protection bit

OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks

ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks

EBTR1 = Table Read Protection bit

OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks

ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks

EBTR2 = Table Read Protection bit

OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks

ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks

EBTR3 = Table Read Protection bit

OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks

ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks

Register: CONFIG7H @ 0x30000D


EBTRB = Boot Block Table Read Protection bit

OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks

ON Boot block (000000-0007FFh) protected from table reads executed in other blocks

Register: IDLOC0 @ 0x200000


Register: IDLOC1 @ 0x200001


Register: IDLOC2 @ 0x200002


Register: IDLOC3 @ 0x200003


Register: IDLOC4 @ 0x200004


Register: IDLOC5 @ 0x200005


Register: IDLOC6 @ 0x200006


Register: IDLOC7 @ 0x200007

 

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安安博客
2015-10-07 11:33
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